1. Field of the Invention
This invention generally relates to analog-to-digital converters (ADCs) and, more particularly, to a system and method for correcting timing errors in an n-path interleaved ADC.
2. Description of the Related Art
An n-path time interleaved ADC consists of n component ADCs operated in parallel and together sampling the signal n times the rate of an individual ADC. In practice, the component ADCs are never truly identical and the sampling clocks they receive can have small phase deviations from the ideal sampling phase. As a result these timing and gain errors produce artifacts which in frequency domain show up as spectral images of the desired signal centered around every multiple of fs/n, where fs is the sampling rate of the composite ADC. If the errors are known they can be corrected with either digital post-processing after the ADC, or with an analog correction circuitry in the ADC, or with some combination of the two.
One way to facilitate the error correction task is to inject a narrow band known test signal into the ADC input, in the background, while the ADC is operating normally, as described in parent application U.S. Pat. No. 8,917,125, which is incorporated herein by reference. This method works well in a two-path case where the test tone produces an image tone, which is also out-of-band and possible to detect with good accuracy. In an n-path time interleaved ADC, one test tone produces (n−1) image tones, which all need to be accurately estimated to extract all the information needed for error calibration.
It would be advantageous if gain and timing errors could be estimated from the statistics of the ADC output signal while the ADC is operating normally, without interjecting a test signal.